Within the data processing industry, there has been much effort directed to increasing the performance of a computer system while at the same time decreasing the overall cost of the system. Among the many variables to be considered in increasing the performance of a data processing system, two very important considerations are the speed of the processor unit or units employed within the computer system and the facility with which data can be transferred from the system memory to the processor unit.
One prior art approach to increasing the performance of a data processing system was to provide a plurality of processor units each connected to the system memory over a common data bus. As an extension of this approach, individual processor units were specifically designed to perform certain types of processor operations very efficiently. Thus, the data processing system might have included a high-speed scientific processor unit specially adapted to perform mathematical calculations at extremely high speeds, a commercial instruction processor unit specially designed to run efficiently operations common in business-related data processing, and a more generalized central processor unit serving as a sort of master processor unit, ultimately controlling the operation of the entire data processing system and also providing additional processing capability.
It is common in such multiple processor data processing systems for each processor to communicate with the system memory through individual couplings to a common data bus. This configuration has significantly increased the processing efficiency of the data processing system and has resulted in a degree of success in increasing the overall performance of the system.
A second approach to maximizing data processing system performance has been to minimize the number of times a processor unit had to access the system memory in order to obtain data stored therein. This approach contemplates the use of a very high speed memory of limited storage capacity called a cache memory. The information most recently requested by the central processor unit is transferred from the systems memory to the cache memory so that subsequent requests for such information results in a transfer directly between the cache and the processing unit withot any need for accessing the slower system memory.
A third approach to increasing the performance of a data processing system has been to employ a hybrid of the first and second approaches and contemplates providing multiple specialized processor unit within the data processor system and employing a cache memory for the controlling processor, e.g., the CPU, among the variety of processors. To a degree, this further increases the performance of the data processing system since the CPU is required to access the system memory fewer times because of the provision of the cache memory and, therefore, the other processor units experience a decrease in the traffic on the data bus with the end result that transfer time from the system memory to the other processor units is reduced.